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Expansion

Peripherals can be connected to the CPU board through the expansion connector, a 96-pin, 3 row DIN41612 right angle connector.

Pinout

  A B C
1 +5V GND +12V
2 +5V GND +12V
3 I2C_SCL1 /I2C_IRQ1 I2C_SDA1
4 GND GND GND
5 GND D8 D13
6 D9 D11 D15
7 D10 D14 D12
8 D7 D5 GND
9 D6 GND D3

10

 GND D4 D1
11 D2 D0 GND
12 GND GND A22
13 A23 GND A19
14 GND A21 A17
15 A20 A15 A18
16 A13 A16 A12
17 A14 A10 GND
18 A11 GND A8
19 GND A9 A6
20 A7 A4 A2
21 A5 A3 A1
22 R/W /LDS /UDS
23 GND /DTACK1 /AS1
24 CLK GND  
25 FC1 FC0 FC2
26      
27     /EXTRST1
28 /EXT5 /BG1 /HALT14
29 /RESET34 /BR1 /BGACK1
30 /IACK1 /IRQ /BERR14
31 GND GND GND
32 SNDR GND SNDL

Note that the data and address bus, as well as most control signals (those in rows 1-25) should be driven through buffers when multiple peripherals are present. These buffers should be direction controlled by the bus request lines, as to allow external bus masters to access CPU board peripherals.

Any empty cells are not currently used and considered reserved for future use, and should be no connect.

Remarks

  1. Pulled up on CPU board
  2. Pulled down on CPU board
  3. Asserted by processor to reset all peripherals. To reset the processor, you must simultaneously assert /RESET and /HALT for at least 1ms.
  4. This signal is open drain.
  5. Asserted when the currently decoded address is valid and is not decoded on the CPU board. Can be used as part of external buffer logic.
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