DMA Channel Allocations

DMAC should operate with dynamic, round-robin priority arbitration within a DMA priority level. Priority levels listed are from 0 (highest) to 3 (lowest.)

• Ch0: Driver I²C Tx (SERCOM3)
  • Priority: 0
• Ch1: Driver I²C Rx (SERCOM3)
  
  • Priority: 0
• Ch2: NOR flash SPI Tx empty (SERCOM5)
  
  • Priority: 1
    
  • Operate in SPI 32 bit data mode
  • Burst transfers
• Ch3: NOR flash SPI Rx complete (SERCOM5)
  • Priority: 1
  • Operate in SPI 32 bit data mode
  • Burst transfers
• Ch4: IO I²C Tx (SERCOM0)
  • Priority: 2
• Ch5: IO I²C Rx (SERCOM0)
  • Priority: 2
• Ch6: Display SPI Tx empty (SERCOM4)
  • Priority: 2
    
  • Operate in SPI 32 bit data mode
  • Burst transfers