Pinout

Using 96 position (3x32) DIN 41612 connectors; right angle male on expansion cards, vertical female on the backplane side.

CPU Board

	A	B	C
1	+5V	GND	+12V
2	+5V	GND	+12V
3	I2C_SCL¹	/I2C_IRQ¹	I2C_SDA¹
4	GND	GND	GND
5	GND	D8	D13
6	D9	D11	D15
7	D10	D14	D12
8	D7	D5	GND
9	D6	GND	D3
10	GND	D4	D1
11	D2	D0	GND
12	GND	GND	A22
13	A23	GND	A19
14	GND	A21	A17
15	A20	A15	A18
16	A13	A16	A12
17	A14	A10	GND
18	A11	GND	A8
19	GND	A9	A6
20	A7	A4	A2
21	A5	A3	A1
22	R/W	/LDS	/UDS
23	GND	/DTACK¹	/AS¹
24	CLK	GND
25	FC1	FC0	FC2
26
27
28	/EXT⁵	/BG¹	/HALT¹⁴
29	/RESET³⁴	/BR¹	/BGACK¹
30	/IACK¹	/IRQ	/BERR¹⁴
31	GND	GND	GND
32	SNDR	GND	SNDL

Note that the data and address bus, as well as most control signals (those in rows 1-25) are driven through buffers, whose direction is controlled by the bus request lines as to allow external bus masters to access CPU board peripherals.

Any empty cells are not currently used and considered reserved for future use.

Remarks:

Pulled up on CPU board
Pulled down on CPU board
Asserted by processor to reset all peripherals. To reset the processor, you must simultaneously assert /HALT for at least 1ms.
This signal is open drain.
Asserted when the currently decoded address is valid and is not decoded on the CPU board. Can be used as part of external buffer logic.